The rapid advancement of printed circuit board (PCB) technologies has fundamentally transformed the electronics industry, enabling devices that would have been impossible to conceive just a decade ago. From the smartphones in our pockets to the 5G infrastructure powering global connectivity, modern PCB innovations have pushed the boundaries of what’s achievable in electronic design. The evolution from rudimentary single-layer boards to sophisticated multi-layer architectures with embedded components represents one of the most significant engineering achievements of the 21st century. As consumer demand for smaller, faster, and more powerful devices continues to accelerate, PCB manufacturers and designers have responded with groundbreaking solutions that address the complex challenges of miniaturisation, thermal management, and signal integrity. Today’s PCBs are not merely platforms for mounting components—they are intricate three-dimensional structures that integrate mechanical, electrical, and thermal functions into remarkably compact form factors.
Evolution from Through-Hole to Surface Mount Technology in PCB Manufacturing
The transition from through-hole technology (THT) to surface mount technology (SMT) represents perhaps the most transformative shift in PCB assembly history. Through-hole mounting, which dominated electronics manufacturing from the 1950s through the 1980s, required drilling holes through the PCB substrate and inserting component leads that were then soldered on the opposite side. While this approach provided excellent mechanical stability, it imposed severe limitations on component density and board complexity. The advent of SMT in the early 1980s revolutionised manufacturing by allowing components to be mounted directly onto the board surface, eliminating the need for drilled holes except for specific applications like high-power connections or mechanical anchoring.
Surface mount technology enabled dramatic reductions in component size—resistors and capacitors that once measured several millimetres in through-hole packages could now be manufactured in sizes as small as 0201 (0.6mm × 0.3mm) or even smaller 01005 packages. This miniaturisation wasn’t merely about size reduction; it fundamentally changed what designers could achieve. Circuit boards could now accommodate exponentially more components in the same footprint, while shorter lead lengths reduced parasitic inductance and capacitance, improving high-frequency performance. The automated pick-and-place machines developed for SMT assembly could position components with extraordinary precision at speeds exceeding 100,000 components per hour, making mass production economically viable for increasingly complex designs.
The manufacturing ecosystem adapted accordingly, with reflow soldering replacing wave soldering as the primary assembly method. Solder paste application through stencils, followed by precise component placement and controlled heating profiles, allowed for consistent, repeatable assembly of densely populated boards. Modern SMT lines incorporate automated optical inspection (AOI) systems that verify placement accuracy and solder joint quality at speeds matching production throughput. However, the transition wasn’t without challenges—smaller components are more susceptible to thermal stress during reflow, tombstoning issues can occur with passive components, and rework becomes progressively more difficult as component sizes decrease. Despite these challenges, SMT has become the de facto standard for consumer electronics, with through-hole technology now reserved primarily for connectors, power components, and applications requiring exceptional mechanical strength.
Recent developments have pushed SMT capabilities even further with the introduction of package-on-package (PoP) and system-in-package (SiP) technologies. PoP stacking allows memory chips to be mounted directly atop application processors, dramatically reducing the PCB footprint required for mobile devices. This vertical integration approach has become essential for smartphones, where every square millimetre of board space commands a premium. Meanwhile, wafer-level chip-scale packages (WLCSP) have eliminated traditional packaging entirely for some applications, with silicon dies featuring solder balls applied directly to the chip surface. These ultra-compact packages measure barely larger than the die itself, representing the ultimate expression of SMT miniaturisation principles. As we look toward future electronics generations, embedded component technology is emerging as the next frontier, integrating passive components within the PCB substrate itself rather than merely mounting them on the surface.
High-Density Interconnect PCBs Enabling Miniaturisation in Smartphones and Wearables
High-density interconnect (HDI) PCB technology has become the cornerstone of modern mobile device design, enabling the remarkable miniaturisation we’ve witnessed in smartphones, tablets, and wearable electronics over the past fifteen years. HDI boards are characterised by finer lines and spaces, smaller vias
and microvias, and higher layer counts than conventional boards, all of which enable far greater routing density within the same or even smaller footprints. Instead of relying solely on mechanically drilled through-holes, HDI PCBs use laser-drilled microvias, buried vias, and blind vias to connect internal layers, reducing the real estate consumed by traditional via pads and annular rings. This allows designers to “fan out” dense BGA (ball grid array) packages such as application processors, RF front-end modules, and memory stacks with remarkable efficiency—critical in devices where every fraction of a millimetre matters. In smartphones and wearables, HDI is what makes it possible to integrate advanced camera systems, high-capacity batteries, multiple radios, and complex sensor arrays into slim, pocketable, and wrist-worn form factors.
Microvia technology and sequential Build-Up processes in apple iphone logic boards
Apple’s iPhone logic boards are a textbook example of how microvia technology and sequential build-up (SBU) processes have revolutionised PCB design for high-end consumer electronics. Rather than building a thick board in a single lamination step, SBU constructs the PCB layer by layer, adding thin dielectric and copper layers that are laser-drilled to create blind and buried microvias between adjacent layers. These microvias often have diameters in the sub-100 micron range, enabling extremely dense interconnects beneath fine-pitch BGA packages like the A‑series SoC and high-bandwidth memory. By using stacked and staggered microvias within the build-up layers, Apple’s designers can route dozens of high-speed signals and power rails in areas that would be impossible with conventional through-holes.
This layered approach also helps optimise signal integrity and power distribution in the iPhone’s compact logic board. Shorter via stubs and tighter loop areas reduce parasitic inductance, which becomes increasingly important as operating frequencies climb into the multi-gigahertz range. At the same time, SBU allows critical nets—such as PCIe, LPDDR, and high-speed display interfaces—to be routed on carefully controlled impedance layers located close to solid reference planes. The result is a logic board that not only fits into an incredibly tight space but also supports the demanding performance, low-jitter clocks, and low-noise power delivery needed for advanced mobile processors and RF systems. For engineers designing compact electronics, adopting microvia and SBU techniques is now less a luxury and more a prerequisite for staying competitive.
Anylayer HDI structures in samsung galaxy flagship devices
Samsung’s Galaxy flagship smartphones showcase another cutting-edge HDI approach: anylayer HDI structures. In a traditional HDI stack-up, microvias typically connect only between specific adjacent layers (for example, from layer 1 to layer 2). Anylayer HDI, by contrast, allows microvias to connect between virtually any pair of layers in the stack-up, greatly increasing routing freedom. This is achieved by carefully controlling dielectric thickness, copper distribution, and lamination cycles so that laser drilling and plating can form reliable inter-layer connections throughout the board. For compact system boards that host application processors, DRAM, NAND, RF transceivers, and power management ICs, this design freedom is invaluable.
Why does this matter for the devices we use every day? In Galaxy smartphones, anylayer HDI makes it possible to bring power and ground connections directly beneath critical components, minimising IR drop and improving thermal spreading. It also enables shorter, more direct routing paths between high-speed interfaces such as UFS storage and the main SoC, which reduces latency and improves overall system responsiveness. Furthermore, anylayer HDI supports tighter component placement, enabling Samsung to integrate larger batteries, more camera modules, and additional sensors without increasing device thickness. For designers working on space-constrained electronics, considering anylayer HDI can unlock routing options that simply don’t exist in conventional multilayer boards.
Stacked via configurations reducing PCB footprint in smartwatch applications
Smartwatches push miniaturisation to the extreme, packing a complete computing platform into a footprint often smaller than a coin. To achieve this, PCB designers rely heavily on stacked via configurations that exploit the vertical dimension of the board. Instead of routing signals laterally across the board, stacked blind and buried microvias allow connections to “dive” through multiple layers in a very small x‑y area. In practice, designers will often place stacked via columns directly beneath major ICs such as system-in-package (SiP) modules or RF transceivers, enabling fan-out within a few square millimetres.
This vertical interconnect strategy dramatically reduces PCB footprint while maintaining robust electrical performance. However, it also introduces manufacturing challenges, particularly with respect to via reliability and plating uniformity. Each stacked via interface must be carefully controlled to avoid voids, cracks, or barrel defects that could compromise long-term reliability under thermal cycling and mechanical stress—conditions that are common in wearables worn during exercise or outdoor activities. For engineers, close collaboration with PCB fabricators is essential: specifying maximum stack heights, via diameters, and aspect ratios up front helps ensure that the design is not only compact but also manufacturable at high yield and capable of surviving years of real-world use.
Laser drilling precision for sub-100 micron via formation
The backbone of HDI manufacturing is laser drilling technology capable of forming microvias with diameters well below 100 microns. Unlike mechanical drills, which are limited by tool wear and bit diameter, UV or CO2 lasers can ablate precise holes in thin dielectric layers without physically contacting the material. This precision allows fabricators to align microvias with copper pads on underlying layers with tolerances in the ±10 micron range—comparable to the thickness of a human hair. Such accuracy is crucial when you consider that a misaligned via can easily short adjacent traces or reduce plating reliability.
From a design perspective, understanding the capabilities and limits of laser drilling is key to successful HDI implementation. Designers must respect minimum via diameters, pad sizes, and capture pad tolerances specified by the fabricator, and should also consider using teardrops or pad-in-pad structures to improve mechanical robustness. As we push towards even finer geometries for next-generation smartphones and AR wearables, laser drilling will continue to be refined, with emerging techniques such as multi-beam systems and advanced registration algorithms improving throughput and alignment accuracy. In essence, laser-drilled microvias function like microscopic elevator shafts in a skyscraper, moving signals vertically through the “floors” of the PCB while occupying minimal horizontal space.
Flexible and Rigid-Flex PCB architectures in foldable display electronics
Foldable smartphones and laptops represent a new frontier where mechanical engineering and PCB technology intersect in unprecedented ways. Traditional rigid boards cannot withstand repeated bending, so designers turn to flexible and rigid-flex PCB architectures to route signals across hinges and folding displays. In a rigid-flex design, one or more rigid sections—hosting dense components and connectors—are interconnected by flexible polyimide-based circuits that can bend thousands of times without failure. This architecture allows the electronics to span moving sections of the device while maintaining reliable connectivity and signal integrity.
Designing for foldable display electronics introduces unique constraints that go beyond standard flex circuits. The bend radius must be carefully controlled, copper thickness optimised, and stress concentrated away from critical traces and vias. At the same time, high-speed interfaces driving OLED or AMOLED panels must traverse these flex regions without excessive impedance variation or crosstalk. The result is a highly specialised class of PCBs that behave more like electromechanical components than traditional flat boards. For product teams exploring foldable or rollable devices, early co-design between mechanical and PCB engineers is essential to avoid costly redesigns later in the development cycle.
Polyimide substrate materials in samsung galaxy fold hinge assemblies
Samsung’s Galaxy Fold series illustrates how advanced polyimide substrates enable robust hinge assemblies in foldable electronics. Polyimide offers an attractive combination of flexibility, thermal stability, and dielectric performance, making it a preferred material for flex circuits that must survive repeated folding. In the Galaxy Fold, polyimide-based flex cables route high-speed display signals and power across the hinge region, enduring thousands of open-close cycles. These substrates maintain dimensional stability even during the high-temperature reflow processes required to attach fine-pitch connectors and components.
Yet not all polyimide materials are created equal. For demanding foldable applications, manufacturers often select low-moisture-absorption, high-tensile-strength grades that minimise the risk of cracking or delamination under mechanical stress. Surface treatments and adhesion promoters further enhance the bond between copper and polyimide, reducing the likelihood of trace lift-off over time. For designers, working closely with material suppliers to understand flexural modulus, glass transition temperatures, and long-term fatigue behaviour can mean the difference between a hinge that feels solid for years and one that fails after a few months of use.
Dynamic flex circuit design for motorola razr folding mechanisms
The modern Motorola Razr foldable phone employs a dynamic flex circuit design that accommodates complex hinge motion, rather than a simple single-axis bend. Unlike a basic “book-style” fold, the Razr’s hinge guides the display and underlying flex circuits through a controlled path that reduces strain on any single point. To support this motion, the flex PCB features carefully defined bend regions with tailored trace routing, staggered conductor placement, and strategic use of “meandering” routes that distribute mechanical stress along the length of the flex.
From a PCB layout perspective, dynamic flex design forces us to think three-dimensionally. Traces carrying high-speed or sensitive signals are positioned closer to the neutral axis of the bend region, where mechanical strain is lowest, while low-speed or redundant connections may occupy outer layers. Vias are avoided in high-strain zones, and copper pour is selectively removed in areas that need to flex more freely. When done well, this approach allows the device to open and close smoothly, much like a precision-engineered watch mechanism, while preserving the electrical performance of the interconnects hidden within.
Copper layer thickness optimisation for bend radius compliance
One of the most critical parameters in flex and rigid-flex PCB design is copper layer thickness, especially in regions subject to repeated bending. Thicker copper layers improve current-carrying capacity and reduce DC resistance, but they also increase stiffness and the risk of cracking under mechanical stress. To meet bend radius requirements—often specified as a multiple of the flex thickness—designers must strike a careful balance between electrical performance and mechanical reliability. For example, a common guideline is to maintain a minimum bend radius of 10 times the total flex thickness for dynamic applications, which typically translates to using thinner copper (such as 12µm or 18µm) in the bend area.
In practice, you might see a design that uses heavier copper in rigid sections for power distribution, then tapers to thinner copper in the flex section that passes through the hinge. Techniques such as “copper thieving” and tapered transitions help avoid abrupt stiffness changes that could create stress concentrations. By simulating bend behaviour and validating prototypes through cyclical bend testing, engineers can confirm that copper thickness choices meet both electrical and mechanical requirements. In many ways, it’s like designing a suspension bridge: you need enough metal to carry the load, but you also need just the right amount of flexibility to cope with movement and stress over time.
Coverlay application techniques protecting flexible circuits from mechanical stress
Coverlay—the flexible equivalent of solder mask—plays a crucial role in protecting flex circuits from mechanical damage, moisture, and chemical exposure. Typically composed of polyimide and adhesive, coverlay is laminated over copper traces, leaving only the necessary openings for pads and test points. In foldable electronics, coverlay application techniques become especially important in high-strain regions, where poorly designed openings or sharp corners can act as crack initiators. Rounded relief openings, gradual transitions, and staggered coverlay overlaps help distribute stress more evenly across the flex surface.
For dynamic flex regions, designers often extend coverlay slightly beyond copper edges to shield trace corners, while avoiding excessive adhesive buildup that could stiffen the flex unnecessarily. In some cases, dual-layer coverlay or selective reinforcement films are used in areas prone to abrasion or contact with mechanical components within the hinge. By treating coverlay design as an integral part of the flex circuit—not just a protective afterthought—you can significantly extend the service life of flexible PCBs in demanding applications like foldable smartphones, medical wearables, and industrial robotics.
Advanced thermal management solutions through embedded copper coin technology
As power densities rise in compact electronics—especially in LED lighting, power converters, and RF power amplifiers—traditional thermal vias and copper pours are often no longer sufficient to keep temperatures under control. Embedded copper coin technology has emerged as a powerful solution, providing a direct, low-resistance thermal path from hot components to external heat sinks or chassis. In this approach, solid copper “coins” or slugs are machined and inserted into cavities within the PCB, then laminated and plated to form an integral part of the board structure. High-power components are mounted directly above these coins, allowing heat to flow efficiently away from the device junction.
Compared to conventional thermal via arrays, copper coins can reduce junction-to-ambient thermal resistance by a significant margin—often by 20–40%, depending on the application and board design. This improvement not only enhances reliability and extends component lifetime but can also unlock higher power output or reduced derating margins, which is critical in applications like automotive LED headlights or 5G RF power modules. Designing with copper coins does, however, introduce additional constraints: board thickness, flatness, and warpage must be carefully controlled, and fabricators need precise milling and bonding processes to ensure consistent results. When implemented correctly, embedded copper coin technology turns the PCB itself into an active thermal management solution, rather than a passive bystander.
Multi-layer PCB Stack-Ups supporting High-Speed signal integrity in 5G infrastructure
5G base stations and network infrastructure demand PCBs that can handle multi-gigabit data rates, complex RF front ends, and stringent timing requirements. Meeting these needs requires carefully engineered multi-layer PCB stack-ups that prioritise controlled impedance, low loss, and robust shielding. Rather than simply adding more layers, designers must think holistically about how each layer contributes to signal integrity, power distribution, and electromagnetic compatibility. Typical 5G infrastructure boards may feature 16 or more layers, combining high-speed digital, RF, and power planes within a single stack-up.
At these frequencies—often extending into the millimetre-wave bands—loss mechanisms that were once negligible become critical. Dielectric loss, copper surface roughness, and via stubs can all degrade signal quality. As a result, engineers must select advanced materials, refine routing strategies, and adopt best practices for via design and ground referencing. When done well, the PCB becomes a stable, predictable transmission medium that supports high-data-rate interfaces such as CPRI/eCPRI, PCIe Gen4/Gen5, and high-speed SerDes links, all while coexisting with sensitive RF paths and power delivery networks.
Controlled impedance design for differential pairs in base station equipment
Controlled impedance design lies at the heart of high-speed PCB layout for 5G base stations. Differential pairs carrying signals like 25G or 56G SerDes must maintain consistent characteristic impedance—typically 85Ω or 100Ω—to minimise reflections, jitter, and eye diagram closure. Achieving this requires precise control over trace width, spacing, dielectric thickness, and copper thickness, all of which are captured in the PCB stack-up and validated through field solver simulations. Even small variations in manufacturing tolerances can shift impedance, so close coordination with the fabricator is essential.
Practical techniques for maintaining controlled impedance include tightly coupling differential pairs, maintaining consistent reference planes beneath high-speed routes, and avoiding abrupt changes in geometry at connectors and vias. Designers often work with layer pairs specifically dedicated to high-speed routing, using symmetrical stack-ups that reduce skew and warpage. In many 5G designs, you’ll also see extensive use of back-drilling to remove via stubs from differential pairs, further improving signal integrity. By treating each differential pair as a carefully tuned transmission line, rather than just two parallel traces, we can ensure reliable performance at the data rates demanded by modern telecom infrastructure.
Low-loss dielectric materials from rogers corporation and isola group
Standard FR‑4 materials struggle to meet the loss and stability requirements of high-frequency 5G systems, particularly in the sub‑6GHz and mmWave bands. To address this, many infrastructure designs now incorporate low-loss dielectric materials from suppliers such as Rogers Corporation and Isola Group. Materials like Rogers RO4350B, RO4003C, or Isola I-Tera MT40 offer lower dielectric loss tangents and more stable dielectric constants across frequency and temperature, significantly improving insertion loss and phase stability for RF and high-speed digital signals.
These advanced laminates can be used in hybrid stack-ups, where RF layers employ Rogers or Isola materials while lower-speed digital and power layers use high-Tg FR‑4 to control costs. However, hybrid constructions demand careful management of CTE (coefficient of thermal expansion) mismatches, lamination parameters, and drilling processes. For designers, the key is to engage early with material vendors and fabricators to define material combinations and process windows that deliver both electrical performance and manufacturability. When properly implemented, low-loss dielectrics can be the difference between a marginal design and a robust, future-proof 5G platform.
Via stub optimisation techniques for Millimetre-Wave frequency applications
At millimetre-wave frequencies, via stubs—the unused portions of plated through-holes—behave like resonant structures that can severely distort signals. Even a fraction of a millimetre of unused via barrel can introduce unwanted impedance discontinuities and resonances within the band of interest. To combat this, engineers employ via stub optimisation techniques such as back-drilling, blind/buried vias, or controlled-depth drilling. Back-drilling, in particular, mechanically removes the unused copper from the via after plating, leaving only the portion needed to connect specific layers.
In mmWave antenna arrays and RF front ends, designers increasingly favour HDI-style blind vias and microvias to minimise stub length from the outset. Careful stack-up planning ensures that signal transitions occur over the shortest possible vertical distance, often between just two or three adjacent layers. Electromagnetic simulation tools can model the impact of via stubs and guide decisions on which nets require optimisation. Although these techniques add complexity and cost, they are often essential for meeting insertion loss and return loss targets at 28GHz, 39GHz, and beyond.
Ground plane referencing strategies minimising crosstalk in dense PCB layouts
Dense multi-layer PCBs used in 5G infrastructure must balance high routing density with strict requirements for low crosstalk and EMI. Effective ground plane referencing strategies are critical to achieving this balance. Ideally, every high-speed signal layer is adjacent to a solid reference plane—usually ground—to provide a low-inductance return path and strong shielding between signal layers. Stitching vias connect these ground planes at regular intervals, forming a Faraday cage-like structure around sensitive traces and components.
In mixed-signal designs that combine high-speed digital, RF, and power circuits, segmentation of ground regions must be done with care. While some isolation between noisy and sensitive domains is beneficial, excessive splits or “moats” in the ground plane can force return currents to take long detours, increasing loop area and radiation. Where ground splits are necessary, controlled bridges and stitching capacitors help maintain a defined return path. By thinking of ground not as an afterthought but as the reference framework around which all signals are routed, designers can significantly reduce crosstalk and improve overall electromagnetic compatibility in complex 5G systems.
Embedded component technology integrating passive devices within PCB substrates
The next leap in PCB miniaturisation and performance is coming from embedded component technology, where passive devices—and, in some cases, even active components—are integrated directly into the PCB substrate. Instead of mounting discrete resistors, capacitors, and inductors on the board surface, these elements are fabricated within internal layers using specialised materials and processes. For example, resistive inks or films can be patterned to form embedded resistors, while thin-film or ceramic materials can create embedded capacitors with very low inductance and excellent high-frequency characteristics.
What does this mean in practical terms? By embedding passives, designers can free up valuable surface area for active ICs, connectors, and mechanical features, directly supporting further device miniaturisation. At the same time, the shorter interconnect lengths and reduced parasitics improve signal integrity and power distribution, particularly in high-speed and RF applications. System-in-package (SiP) modules for smartphones, wearables, and IoT devices increasingly rely on embedded components to achieve their compact form factors and performance targets. However, embedded technology also introduces new challenges in testing, rework, and yield management, since faulty embedded elements cannot simply be replaced like discrete components.
To successfully adopt embedded component technology, engineers and manufacturers must invest in advanced design tools that can model these integrated structures, as well as fabrication processes capable of tight tolerance control. Design-for-test (DFT) strategies need to evolve to accommodate internal components, often relying more heavily on boundary scan, built-in self-test (BIST), and advanced inspection techniques. As these capabilities mature and costs continue to fall, we can expect embedded components to become increasingly common in mainstream PCB designs, enabling even slimmer smartphones, more capable wearables, and highly integrated modules for automotive and industrial electronics. In essence, the PCB is transforming from a passive interconnect platform into an active, functional part of the electronic system itself.